• Results List

The primary purpose of the Results List is to display compilation information and design errors uncovered during compilation. The Results List is also used for accumulating search results.

Compilation warnings and errors are displayed in a hierarchical structure. If the warning or error concerns a schematic or state diagram then the descriptive text will appear under the schematic or state diagram it is associated with. If the warning or error concerns a particular component instance on a schematic or state diagram then the descriptive text will appear under both the schematic or state diagram and the component instance, in a hierarchical fashion. Clicking on the descriptive text will move the focus of the Design Canvas to the schematic in question. If the error or warning was concerning a particular component instance, that instance will be highlighted with a red rectangle. The red rectangle will disappear as soon as the mouse cursor is moved over the Design Canvas.

• The stages of compilation

At the start of each compilation stage a message is appended to the Results List to inform the user the stage has begun. There are 7 major stages during compilation which are:

1. Processing built in components - Writes VHDL for built in components to the compiler temporary directory
2. Processing user schematics - Writes VHDL for user defined schematics to the compiler temporary directory
3. Performing synthesis - Calls the Xilinx synthesis tool
4. Building database - Calls the Xilinx NGDBuild tool
5. Mapping design - Calls the Xilinx mapping tool
6. Routing design - Calls the Xilinx placement and routing tool
7. Generating bitstream - Generates the downloadable image

• Search Results