What Interactive Logic does for you Interactive Logic simplifies the task of implementing digital logic. It is very much like an integrated compiler, debugger, and operating system, albeit for use with hardware rather than software. Like its software equivalent, it does many things including taking care of common house-keeping issues and standardizing the approach to common requirements. Interactive Logic simplifies what you need to do to achieve your objective of getting a logic circuit working in an FPGA. Interactive Logic transparently- translates your circuit into the VHDL hardware description language so that it can be compiled into a bit pattern for configuring the FPGA. You do not need to see or understand the VHDL. takes care of all the settings and the multi-step process for Logic Module FPGA circuit compilation and configuration, thereby simplifying the design environment. integrates the necessary data access circuits into your logic, keeps track of the data locations, maps the terminals on your schematic directly to Logic Module I/O pins, and handles data access in the background. provides the processes and support circuits required to control the running and pausing of your circuits, to set the frequency of the system clock, and to provide timebase signals. Interactive Logic also - displays the logic data and signals on your schematics, or in waveform style displays, even if the data and signals are hidden multiple levels down in sub-schematics. You can even enter new data values while the circuit runs. provides a library of components compatible with the data access requirements, and enables you to design sub-systems, components, and their associated symbols which may also display circuit data. provides a means of determining the maximum clock frequency that your circuit will run without error. enables you to generate a C++, C#, or Java library so that you can write programs for a PC to access the data in a Logic Module while it is running. Interactive Logic supports all of these facilities within a simple integrated environment with easy-to-understand procedures, and without you having to understand the details of what is happening in the background. In the simplest case, all you have to do is draw your schematics, press one button to compile the project, one to download it, and another to run it.
Standardization Doing all of this requires some standardization of the circuits you implement in a Logic Module - All input signals are sampled and latched each positive edge of the clock by flip-flops in the input ‘terminals’ you use on your schematics. This provides protection against meta-stability caused by asynchronous input signals, but introduces a one clock delay in the input signal available to your circuit. As is normal with FPGA circuits, the clock is distributed via a special global network in the FPGA designed to minimize clock skew. Control as to whether a flip-flop will sample its input on any particular clock pulse is achieved via a Clock Enable input on each flip-flop. All Interactive Logic flip-flops are synchronous and their clock pins are automatically connected and hidden rather than being shown on the logic diagrams. Accessing the logic data cannot be done without interrupting the operation of the circuit to some extent. When the software needs to update the display, or otherwise access the data, it briefly pauses the clock used by your circuits. A dedicated output is provided to signal to any circuits external to the Logic Module when this happens so that the external circuits can accommodate to the interruption. Reading the data in a circuit with 200 or 300 flip-flops, for example, may require a data access interruption of 500us. After the data is read, your circuit will resume operation from the exact same circuit state that existed prior to the interruption. There is more discussion of this subject, including ways of overcoming this limitation in Debugging. All output signals are latched each positive edge of the clock before routing to the output pins. The latches serve to maintain the output levels during the data access interruption and ensure clean glitch-free outputs at all times.
Comms Card The microprocessor on the Communications (Comms) Card manages overall control and data access for the software. Communications from the PC running the Interactive Logic software to the Comms Card operates at 10MHz or 100MHz using TCP/IP via a standard Ethernet network setup or a crossover cable. We suggest you see the QuickStart Guide for set-up instructions and the Network Hardware Configuration document for detailed information on setting IP Addresses.
Running with the Comms Card removed The system is designed so that the Comms Card can be removed if the link to a PC is not needed and the Logic Module may be left to run its application by itself after it is debugged. You set this up by - using Interactive Logic to write the circuit configuration into the Flash ROM on the Logic Module, turning the power off and removing the Comms Card, removing the No Load From ROM jumper, and turning the power back on again. The Logic Module will automatically load and run the circuit in the Flash ROM when the power comes on. Please note that the only purpose of writing the circuit configuration into the Flash ROM on the Logic Module is to enable automatic start-up at power-on. You do not have to write the circuit into ROM to run it via Interactive Logic, so development downloads do not use up Flash ROM programming cycles.
Versions of the Comms Card During debug you run with the Comms Card plugged in, and must use the Development Version of the Comms Card which enables you to use full debug facilities with the Logic Module. A lower cost Runtime Version is also available and is intended to be left in place to enable operation to be monitored, data to be read and written, and field upgrades to be downloaded to your circuit. It does not support debugging. The purpose of the Runtime Version is to offer a lower cost alternative to customers who wish to deploy multiple systems, but do not need development facilities on them all. The Development version supports everything supported by the Runtime Version, plus the ability to debug your circuits.
I/O The Logic Module has six twenty pin headers, each of which has sixteen I/O pins and four 0 Volt pins. The 0 Volt pins are pins 3, 8, 13, and 18. The I/O pins can be software selected as inputs, outputs or I/O. The output buffer is a tri-state buffer. I/O pins are identified on your schematics by header and pin numbers. Header 5, pin 11, for example, is identified as JP_5_11, and is selected from a pull-down list. You do not need to be involved with FPGA pin numbers, or even type the “JP_5_11”.
Clock The Logic Module has an on-board 100 ppm 50MHz Crystal Oscillator and a Phase Locked Loop (PLL) with appropriate counter circuits. The PLL can generate 86 different clock frequencies at intervals of 2 to 4% between 10MHz and 100MHz. For example - 10.0, 10.25, 10.5, …48, 49, 50, 52, 54, … 96.0, 98.0, 100MHz. The clock frequency is selected via software and stored as part of the project information used to configure the Logic Module. The selected frequency is established prior to start-up even in the absence of a Comms Card.
Timebase Three Crystal Oscillator derived Timebase signals with 1us, 1ms and one second periods are provided as library items for use in your circuits. These signals are synchronized with the FPGA clock, whichever clock frequency you select, and timebase pulses last for one clock cycle, which allows them to be used to directly enable a counter to count once per timebase period.
Multi-level Schematic Editor The Schematic Editor for entering projects is organized around a project tree much like the directory tree displayed by Windows Explorer. The Built-in Library provides you basic components for use on your schematics, and is shown as an integral part of the project tree together with any sub-schematics you have added to the project. The Schematic Editor enables you to drag components directly out of the library onto your schematics. An auto-router and rubber-banding make wiring your circuit easy. Any project consists of a top-level schematic which references all the circuits and sub-schematics to a single drawing. From there, you can drill down into the design by double clicking on any of the symbols present to see the detail encapsulated by the symbol. The multi-level features are illustrated by the demonstration program loaded into the flash memory of each Logic Module shipped. When you draw a sub-schematic you also produce a symbol representing it for use on higher level schematics. A default symbol is produced automatically, but you can use the Symbol Editor to modify or redraw it to suit your own needs, and you can control the default placement of symbol inputs and outputs by your placement of the inputs and outputs on your sub-schematic. To modify a symbol, just display the schematic that the symbol represents on the Design Canvas by double-clicking it in the Project Tree, and press the Symbol Editor button to open the Symbol Editor. The Symbol Editor, as well as enabling you to customize symbol graphics, also enables you to display data from the underlying schematics on the symbol. Counters can display the number they contain for example. Input and output terminals on the top level schematic represent Logic Module I/O connections and are identified by Logic Module connector numbers. Input and output terminals on a sub-schematic correspond to the inputs and outputs on its associated symbol. When you want to place a sub-schematic symbol you simply select the name of the sub-schematic in the project tree and drag it onto your schematic. The symbol will appear and you can drop it where you wish. You can view and edit the top level schematic or any sub-schematic by double clicking its name in the project tree. At present the library contains basic logic elements, counters up to 32 bits, test functions, terminals and bus splitters/combiners, and will be enlarged in due course. You can easily add your own designs to the library. You can use a symbol as many times as you require, and each additional time you use it you will add another instance of the circuit it represents connected into the system as you have connected the symbol. Any sub-schematic can have further sub-schematics as component parts, and nesting is only limited by the size of the FPGA.
The Offline and Online Project Trees If you use a symbol in several places when you enter and edit your design, the circuits represented by the symbol are always the same. The symbol in the library represents a type of circuit, rather than an instance of a type, and so the sub-schematic is only shown once in the Offline Project Tree. That is not the case when you have downloaded your circuit and are viewing and monitoring the schematics online as they represent the actual circuit in the FPGA. Although all sub-schematic instances are still identical as far as circuit design is concerned, they actually represent different sections of FPGA circuitry and the data can be expected to differ, instance to instance. In this situation what you want is access to each individual instance, particularly so that you can display and modify the circuit data in the context of the circuit, or get access to signals. To give you access, each individual instance appears separately in the Online Project Tree, structured as per your circuit so you can select any instance and view the data associated with it. The Built-in Library is also omitted from the Online Project Tree, because the circuit cannot be edited during monitoring, and the internals of library components are not accessible. While online, you can access the top level schematic or any instance of a sub-schematic by clicking its name in the online project tree. |